1. Field of the Invention
This invention relates to computer circuit layout and, more particularly, to methods and apparatus for automating and providing more effective computer circuit layout design.
2. History of the Prior Art
Computer circuits are designed, developed, and tested by computer circuit designers. Once the design is completed, the circuits must be laid out through some kind of layout graphics editor. Generally, this layout is done by a software tool which uses a standard library of circuit elements and a schematic diagram provided by the circuit designer to generate a layout. Typically, this layout is designed to provide the shortest overall connection between circuit elements. Such a tool is referred to as a place and route tool. A typical tool is "Place and Route" manufactured by Cadence Design Systems, Inc. and described in Cadence, Place and Route Reference Manual, Version 2.0, Jun. 22, 1988. Another such tool is "CAL-MP" manufactured by Silvar-Lisco, Mento Park, Calif.
The layout area available and the circuit schematic diagram to be placed on the area are furnished as inputs to the tool. The tool uses a library of standard circuit cells to place the circuit elements shown in the circuit diagram and to connect those elements according to the circuit diagram. Typically, such a tool produces a circuit layout in which the combinatorial circuit elements (gates) are interspersed with the sequential circuit elements (flip-flops and latches). Once the layout has been produced, certain design elements must be added. For example, it is not until the layout exists that the length of the metal connecting various elements is known; and it is only when the length is known that the buffers for driving circuit elements may be determined. Essentially, it is necessary to first use the tool to plot the layout and then individually design the buffers after computing all of the paths and the lengths of metal. This is very time consuming and, thus, expensive work. The typical layout produced by a place and route tool makes this very difficult because the length of individual metal conductors must be computed, for example, in order to determine the degree of amplication that individual buffers must produce. This makes the design of the buffers which drive signals to the sequential elements such as flip-flops difficult.
Another problem encountered in using place and route tools is that the circuitry, once designed and laid out, must be tested to make sure it functions correctly. This means that testing procedures are necessary to determine the integrity of the individual elements and their interconnections. These testing procedures often require additional metallic conductors be connected between the elements of the chip. In general, the circuit elements are placed by the place and route tool based on the shortest possible interconnect lines which are to be used in the operating circuitry without any reference to testing procedures or connections required by those procedures. Then, after the elements are placed, it is necessary for a designer to go back and individually plot out the connections necessary to accomplish the testing. Once again, this is difficult, time consuming, and therefore expensive work. Moreover, it is not work which allows the length of the metallic connectors used for testing to be minimized.